Timer subsystem for use with data processors have been relatively common for a number of years in both stand-alone and integrated form. The timer subsystem of the 6801 microcomputer available from Motorola is an example typical of prior art timer subsystems. In the 6801, a single free-running counter which is driven by the system clock provides the reference for two separate timer functions. Input timer functions, in which the state of the counter is captured in response to an input to the timer subsystem, and output functions, in which an output of the timer is triggered when the counter reaches a pre-selected count, are both possible on the 6801.
The 6801 timer subsystem is also typical of prior art systems in that a substantial burden is placed on the host processor in order to perform useful timing functions. For instance, in an engine controller application, an input function is typically required to determine the crankshaft angle and an output function is required to perform ignition timing and/or fuel injection. The host processor must continuously respond to interrupts generated by the input capture circuits, perform necessary calculations and set up the next output function. As the number and complexity of the timing functions required increases, the capacity of the host processor to meet the increased timer service overhead is, at some point, exceeded.
This burden on the host processor has been increased as the number of channels of timer functions has increased. For instance, the MC68HC11A8 microcomputer, also available from Motorola, has three capture-only channels and five match-only channels. However, the architecture of the individual channels has not evolved significantly in a way that can reduce the burden on the host processor.